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[Other resource] crc_verilog_xilinx

Description: CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Platform: | Size: 10947 | Author: 李鹏 | Hits:

[Applications] crc_verilog

Description: 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
Platform: | Size: 10752 | Author: 刘波 | Hits:

[Other resource] crc

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写
Platform: | Size: 819 | Author: 宋子奇 | Hits:

[Applications] crc_verilog

Description: 用于计算CRC的verilog HDL源码-CRC calculation for the Verilog HDL source
Platform: | Size: 10240 | Author: 刘波 | Hits:

[VHDL-FPGA-Verilog] CRC校验参考设计_xilinx_vhdl

Description: 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
Platform: | Size: 49152 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Platform: | Size: 10240 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] crc_16

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[Other] desigingCRCwithVDHL

Description: 用VHDL设计CRC发生器和校验器，供初学者参考。-CRC generator and calibration device for advanced users.
Platform: | Size: 112640 | Author: 小山 | Hits:

[VHDL-FPGA-Verilog] CRC32_VHDL_SOURCE_CODE

Description: 这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature
Platform: | Size: 7168 | Author: 黎飞飞 | Hits:

[VHDL-FPGA-Verilog] CRC_VHDL

Description: 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
Platform: | Size: 204800 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] crc_32_16

Description: crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
Platform: | Size: 296960 | Author: likj | Hits:

[MiddleWare] crc

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用verilog HDL编写-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared using verilog HDL
Platform: | Size: 1024 | Author: 宋子奇 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] crc7_4

Description: 使用Verilog HDL语言按标准编写的CRC（7,4）循环码，对学习编码有很好的指导作用！-Verilog HDL CRC(7,4) coding
Platform: | Size: 193536 | Author: caizhixiang | Hits:

[Other] CRC16_8

Description: 利用ISE软件采用Verilog HDL语言编写CRC码，每时钟处理8bit数据，在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
Platform: | Size: 3329024 | Author: 刘璐 | Hits:

[Software Engineering] crc32

Description: crc-32 主要用于网络传输中的 检测，防止错误数据传输-verilog hdl
Platform: | Size: 3072 | Author: fengsen | Hits:

[VHDL-FPGA-Verilog] crc-16b-parallel

Description: CRC generator in verilog hdl
Platform: | Size: 1024 | Author: Srikanth | Hits:

[VHDL-FPGA-Verilog] crc_nguyenquanicd

Description: design crc module in data network transmission
Platform: | Size: 2048 | Author: Zick | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

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